Functional Verification

Verification effort consumes over 55% of the IC Design effort and requires an increasing adoption of verification technologies within FPGA projects[1]. Having the right functional verification approach which is depending on your project is now an essential.

With strong expertise in this domain, AEDVICES Consulting helps you define your verification approach, architect a proper verification environment and develop the appropriate test suite to hit your goals. Whether your project is driven by time to market, or by a formal requirement tracking process such as DO-254 and ISO26262, we can find the best approach to support your project.

Our expertise is based on 3 elements:Verification Expertise by AEDVICES Consulting

Verification Methodologies
  Requirement Based Verification
  Assertion Based Verification
  Coverage/Metrics Driven
  Graph Based

Verification Technologies
  SystemVerilof/UVM
  Specman
  VHDL/Verilog/SystemC
  Scripting: Python, Perl, …

Project Types
  IP, Subsystems, CPU, DSP
  Systems, SoC
  Hw/Sw co-verification
  Firmware verification
  Application
  Tool assessment and qualification

Member of Mentor Graphics Questa Vanguard Program we strongly follow the latest advances in stimuli generation, UVM and portable stimulus standards.

As a OneSpin Spinnaker member, we also follow the latest technology adoptions in formal verification, fault tolerant systems and theorem proving.

Our team can jump on your existing projects, or develop the entire verification process starting from the verification plan through to the verification closure.

CIR - Crédit Impôt RechercheAEDVICES Consulting is certified by the Ministry of Higher Education, Research and Innovation as company qualified to realise R&D for other companies (CIR program).

 

Contact us for more information

[1] Wilson Research Group Functional Verification Study – 2016