Adrien Carmagnat of AEDVICES on Functional Safety at DVCon Europe


Adrien Carmagnat, AEDVICES’ latest recruit and an expert in verification methodologies, presented a paper on Keeping up with rapidly advancing safety standards at DVCon Europe in Munich last month (2018 Proceedings will be made available late January on the DVCon website).

AEDVICES Consulting is still recruiting new employees and trainees. If you would like to become our next new talent, please feel free to apply!

Adrien Carmagnat – DVCon Europe 2018

We were particularly pleased to present this work since (we believe) it makes a significant contribution to industry discussions on safety standards, and especially the part that Functional Verification has to play.

Furthermore, it is the fruition of an excellent collaboration with our customer, Melexis, and it’s been a great professional development experience for Adrien.

Adrien started as a trainee within AEDVICES Consulting eight months ago having majored in Embedded Systems at Polytech’Sophia. He has been trained on Advanced Verification Methodologies and during his internship he also developed skills in Verification IP and Tool Qualification. To recognise his excellent contribution to the project, we asked Adrien to step up to the plate and make the DVCon presentation, knowing there was a lot of verification expertise in the audience and that this would be a challenge!

Adrien was proud to make the presentation (and a bit nervous, too!). As he said afterwards: “I went on stage with a bit of stress, but it turned out to be easier than I’d expected! The attendees seemed interested. They asked probing questions and even shared some ideas that are prompting me to dig deeper into the subject. They may be useful for another paper next year – who knows! “



AEDVICES Consulting and ICONDA Solutions are coming together

AEDVICES Consulting, specialist in functional verification services, trainings and IP, is happy to welcome Andrew Betts as its new partner. He is joining our team to support functional verification sales and to strengthen our trainings catalogue.

Andrew is the owner of ICONDA Solutions and provides consulting, tranings and events for customer-facing teams.

This new collaboration is based on the reflexion that both activities are complementary. With AEDVICES Consulting’s expertise in functional verification and ICONDA’s expertise in many forms of trainings and facilitation, we hope to create a new synergy.

Presentation at DVCon Europe 2018

Adrien CARMAGNAT and François CERISIER, will present their paper during the new edition of DVCon Europe.

The Design and Verification Conference (DVCon) Europe is the leading European event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. This year, DVCon Europe will be held in Munich from October 24 to October 25.

To attend AEDVICES’ presentation:

Qualification of a Verification IP under Requirement based Verification standards: An Approach to the Verification of the Verification
Thursday October 25, 3:15pm – 4:45pm | Forum 5
Functional Safety Session

More information and registration : DVCon Europe website

Launch of the Galactic Partner Program from Breker Verification Systems

With long term relationship with Breker, AEDVICES Consulting is proud to  be part of this this Galactic program to enable the adoption of the Portable Stimulus Standard.

Breker Verification Systems Forms Galactic Partner Program to Accelerate Portable Stimulus Standard Ecosystem

Inaugural Consulting and Training Partners Include AEDVICES Consulting, Axiomise, Sunburst Design, T&VS, Willamette HDL

SAN JOSE, CALIF. –– May 2, 2018 –– Breker Verification Systems, the leading provider of Portable Stimulus, today announced formation of its Galactic™ Partner Program, naming five inaugural consulting and training companies to help accelerate the Portable Stimulus Standard Ecosystem.

The inaugural partners are AEDVICES ConsultingAxiomiseSunburst DesignTest and Verification Solutions (T&VS) and Willamette HDL, all recognized verification experts who manage and support large chip design and verification projects. Under terms of the program, each will work to build the ecosystem around the upcoming Accellera Portable Stimulus Standard, a standard means of specifying verification intent and behaviors reusable across target platforms, using the Breker tool suite.

Specifically, Sunburst Design and Willamette HDL will become Portable Stimulus Standard trainers based on the Breker tool suite, while AEDVICES Consulting, Axiomise, and T&VS will offer verification consulting services also based on TrekSoC™ and TrekUVM™.

“As the Portable Stimulus Standard moves fully into the verification flow, it becomes critically important to have experts available to help further adoption,” states Adnan Hamid, Breker’s founder and chief executive officer. “We selected the best-known and regarded industry experts to train the users about the value and benefits of Portable Stimulus.”

Future announcements about Breker’s Galactic Partner Program will include new members who supply verification intellectual property (VIP) and tools. For more information about the Galactic Partner Program, visit:

Breker first introduced a graph-based approach to test case generation in 2008, now known as Portable Stimulus. It gives chip design verification groups true Verification GPS (Graph-based, Portable, Shareable) with its Portable Stimulus solutions. Through the use of a Graph-based intent specification in an industry standard language, TrekSoC and TrekUVM offers proven Portability across verification platforms, scaling from IP to SoC for vertical reuse and SoC to post-silicon for horizontal reuse. It is Shareable across global diverse teams, project revisions and communication channels.

Breker’s tool suite is in use at large and mid-sized semiconductor companies worldwide on a variety of projects, including universal verification methodology (UVM) sequence synthesis and software-driven test generation from easy-to-author, graph-based representations and hardware/software scenario generation for emulation and system tests. Applications range from servers, networking, graphics processing units (GPUs) and field programmable gate arrays (FPGAs) to mobile and base stations for cellular wireless.
Breker is a founding member and an active participant of the Accellera Portable Stimulus Working Group (PSWG) and contributed a working C++ language representation for standardization efforts.

About Breker Verification Systems
Breker Verification Systems is the leading provider of Portable Stimulus solutions, a standard means to specify verification intent and behaviors reusable across target platforms, and the first company to introduce graph-based verification. Its Portable Stimulus suite of tools is Graph-based to make complex scenarios comprehensible, Portable, eliminating test redundancy across process, and Shareable to foster communication and reuse giving chip design verification groups true Verification GPS. Breker is privately held.

Trainings brochure 2018 is now available

Verification methodology and SystemC/TLM trainingsAre you looking for trainings in Verification Methodologies or SystemC/TLM?

Our trainings brochure is now available and can be downloaded here.


The trainings proposed by AEDVICES Consulting are oriented for:
Design engineers with verification activities
Verification engineers who want to reinforce their methodology knowledge
Team leaders who need verification comprehension

With over 18 years experience on the fields of IC Design Verification and Modeling and recognized as experts in their domains, our trainers will provide adapted trainings to better reach your demands.

Contact us for information or a quotation.

Referenced by Datadock, French companies can contact their OPCA to obtain funding for our trainings.

Mentor User2User Conference : a great technical event

Aedvices Consulting's presentation at Mentor U2U Europe ConferenceMentor User2User Europe Conference – a one-day conference and exhibition dedicated to end-users of Mentor EDA solutions – was very successful. The presentations were of good quality and very interesting.

Francois Cerisier, Aedvices Consulting's CEOAs a Questa Vanguard program partner, Aedvices Consulting was invited to present during the event. In the SoC Verification track, Francois Cerisier presented “Applying Continuous Integration to Hardware Design & Verification” in front of a panel of verification engineers up to design managers in IoT, avionics or automotive. This has been well received and interesting questions were raised.

Good contacts were made during the breaks and the evening event. And it is always a pleasure to gather great technical discussions with industrials and other companies.

Presentation during U2U Europe

U2U Europe

The new Mentor User Conference, USer2User Europe (U2U Europe), will be held in Munich on November 27, 2017.


During this event, technical experts will present the latest advances in their domain. 

U2U Europe focuses on four key areas:

  • IC Design & Test
  • Functional Verification and Emulation
  • Analog Mixed-signal & Physical Verification
  • PCB Design & Analysis

François Cerisier, CEO of Aedvices Consulting, will present his paper “Applying Continuous Integration to Hardware Design and Verification” Track Functional Verification, Salon Cezanne, at 4:00pm

Take also the opportunity to meet us during the all day and the evening network event.

SAFE-Air 2017-2022 Project is looking for a PhD Student

Subject : Safety Evaluation of Aircraft Systems using Virtual Platforms

Confronted with increasingly stringent requirements for certification in operational safety, companies in the field of transport are looking for new methods to assess the robustness of complex digital integrated systems. In particular, our industrial partners in this project, THALES Valence and AEDVICES Consulting, are interested in the robustness of flight systems used in aeronautics. Integrated systems, due to the evolution of technologies, are increasingly sensitive to disturbances caused, for example, by atmospheric particles. Beyond aeronautical systems and transport systems in general (automotive, railway, etc.), the results of this project concern all the integrated systems used in critical applications: energy generation systems (nuclear power plant), medical implants…

The aim of the thesis is to propose a new approach to allow a more precise evaluation of the level of robustness of critical complex digital systems very early in development.

This project is part of the AURA (Auvergne Rhône Alpes) region’s “DIGITAL” and “MOBILITY, INTELLIGENT TRANSPORT SYSTEMS” areas of excellence. It is also part of the MINALOGIC competitiveness cluster.

The PhD student will be located within the LCIS laboratory in Valence (26). The thesis will be supervised by professors from three laboratories: LCIS, TIMA (Grenoble), and LHC (Saint Etienne).
How to Apply
Applicants must hold a Master (or equivalent) in Computer Science, Embedded System or Microelectronics.
Candidates must send a CV, a letter of motivation, details of the grades for each master courses and the classification in master years, and at least one letter of recommendation.

Details of the PhD Subject Safety Evaluation of Aircraft Systems using Virtual Platforms

VerifWorks and AEDVICES Consulting will present during DVCon India 2017

VerifWorks and Aedvices Consulting has collaborated to propose a paper during DVCon India 2017.

The paper “Adding Agility to Hardware Design-Verification using UVM & Assertions – with Jenkins for Continuous Integration” will be presented by Srujana Reddy on Friday, September 15 during the “DV Papers : Regression” Session (4:00pm to 5:30pm).

This paper presents the main differences between software development and hardware verification in terms of integration process, with an emphasis of the hardware development constraints which make the Continuous Integration flow not directly applicable.

It will then present how to adapt the Continuous Integration paradigms to hardware design and verification in order to minimize the integration feedback loop, increase status visibility while still keeping a coverage driven verification, requirement based verification and assertion based verification approach in mind. This paper also illustrates how a Continuous Integration tool such as Jenkins can be used to enhance project visibility, based on the user experience of adopting this approach on to a couple of projects for the Space Industry and in the IoT domains.

DVCon India is a 2-day event attended by industry leaders, system architects, verification experts, SoC integrators, chip designers, IP developers, VIP developers and firmware engineers. The conference has onel track dedicated to Design & Verification languages, methodologies based on SystemVerilog, Verilog, UVM and technologies such as Formal Verification, Hardware Acceleration, Emulation and prototyping, along with the most widely used simulation and more.