Trainings brochure 2018 is now available

Verification methodology and SystemC/TLM trainingsAre you looking for trainings in Verification Methodologies or SystemC/TLM?

Our trainings brochure is now available and can be downloaded here.

 

The trainings proposed by AEDVICES Consulting are oriented for:
Design engineers with verification activities
Verification engineers who want to reinforce their methodology knowledge
Team leaders who need verification comprehension

With over 18 years experience on the fields of IC Design Verification and Modeling and recognized as experts in their domains, our trainers will provide adapted trainings to better reach your demands.

Contact us for information or a quotation.

Referenced by Datadock, French companies can contact their OPCA to obtain funding for our trainings.

VerifWorks and AEDVICES Consulting will present during DVCon India 2017

VerifWorks and Aedvices Consulting has collaborated to propose a paper during DVCon India 2017.

The paper “Adding Agility to Hardware Design-Verification using UVM & Assertions – with Jenkins for Continuous Integration” will be presented by Srujana Reddy on Friday, September 15 during the “DV Papers : Regression” Session (4:00pm to 5:30pm).

This paper presents the main differences between software development and hardware verification in terms of integration process, with an emphasis of the hardware development constraints which make the Continuous Integration flow not directly applicable.

It will then present how to adapt the Continuous Integration paradigms to hardware design and verification in order to minimize the integration feedback loop, increase status visibility while still keeping a coverage driven verification, requirement based verification and assertion based verification approach in mind. This paper also illustrates how a Continuous Integration tool such as Jenkins can be used to enhance project visibility, based on the user experience of adopting this approach on to a couple of projects for the Space Industry and in the IoT domains.

DVCon India is a 2-day event attended by industry leaders, system architects, verification experts, SoC integrators, chip designers, IP developers, VIP developers and firmware engineers. The conference has onel track dedicated to Design & Verification languages, methodologies based on SystemVerilog, Verilog, UVM and technologies such as Formal Verification, Hardware Acceleration, Emulation and prototyping, along with the most widely used simulation and more.

AEDVICES Consulting recrute un ingénieur en vérification hardware

Ingénieur consultant(e) en vérification, vous intervenez sur les projets clients en vérification fonctionnelle et mise en place des méthodologies et environnements de vérification. Vous serez aussi amené(e) à intervenir sur les développements internes (IP de vérification, flots, démonstrateur sur plateforme SoC/FPGA).

Encadré(e) par un expert en vérification et un expert en design/FPGA, vous serez, en fonction de votre profile, formé(e) et coaché(e) aux approches et méthodologies nécessaires à votre mission, pour ainsi évoluer vers une expertise technique à forte valeur ajoutée.

Poste basé à Moirans (38) -proche Grenoble-, vous êtes amené(e) à intervenir ponctuellement chez nos clients en France et en Europe.

Profile
De formation ingénieur ou équivalent, vous avez une sensibilité technique à la fois hardware et software.

Une première expérience ou un stage significatif en design ou en vérification vous permet d’appréhender les problèmes techniques d’un système sur puce ainsi que la compréhension de spécifications clients.

Compétences Clés

Maitrise des langages de conception VHDL et Verilog
Architecture des Systèmes FPGA et/ou System-On-Chip
Compréhension des protocoles de bus de communication SoC
Programmation Objet (C++ / Java ou autre)
Scripting (TCL, Perl, Python, …)
Anglais
Compétences Additionnelles

Connaissances minimales en SystemVerilog
UVM
Connaissances des protocoles AMBA (AHB, APB, AXI), SPI, I2C, UART, Ethernet, USB, PCI, …
Programmation Software bas niveau, driver, RT-OS (assembleur, C)
Flots FPGA (Xilinx, Altera, MicroSemi, …)
Méthodologie de test et de vérification fonctionnelle
SystemC

AEDVICES Consulting joins Mentor Graphics Questa Vanguard Program

 

AEDVICES Consulting joins Questa Vanguard Program, enabling high level verification services and expertise on Mentor Questa products, SystemVerilog, UVM, intelligent testbench.

The Questa Vanguard Program (QVP) extends Mentor Graphics’ breadth of design and verification technologies through partnerships with industry-leading companies. QVP partners provide verification related tools and methods, verification IP, conversion services, training and consulting based on Mentor Graphics industry leading Questa verification platform.  The program was established to bring design and verification engineers world-class product integrations and interoperability to enhance their Questa verification options and build a strong and comprehensive SystemVerilog ecosystem.