AEDVICES Consulting develops and provides quality verification IPs (VIP). Designed with full debug, full functional coverage and full protocol checkers, our VIPs will leverage your verification tasks and speed up your verification process. Based on SystemVerilog and UVM, our VIPs fully integrate in your SystemVerilog/UVM flow without complex integration and compilation flow. We also deliver easy to use Verilog tasks so that even designers can use our VIPs for directed testing.
Our VIPs will accelerate your verification tasks in the fields of Network-On-Chip, Cache Coherency, SoC embedded bus protocols as well as SoC IOs protocols.
As a Member of Mentor Graphics Vanguard Program, our VIPs are fully tested with Questa Prime and Questa Ultra, both on Linux and Windows. Other SystemVerilog simulators are also supported.
Key Advantages of our Verification IP:
Source code availability
Fully SystemVerliog/UVM compliant
Requirement Based Verification IP
Example of Available Verification IP:
AXI 3 & 4, AXI-ACE, CHI, ATB
Generic NoC Verification IP
I2C, UART, SPI, JTAG
Under development or On-demand