VerifWorks and AEDVICES Consulting will present during DVCon India 2017

VerifWorks and Aedvices Consulting has collaborated to propose a paper during DVCon India 2017.

The paper “Adding Agility to Hardware Design-Verification using UVM & Assertions – with Jenkins for Continuous Integration” will be presented by Srujana Reddy on Friday, September 15 during the “DV Papers : Regression” Session (4:00pm to 5:30pm).

This paper presents the main differences between software development and hardware verification in terms of integration process, with an emphasis of the hardware development constraints which make the Continuous Integration flow not directly applicable.

It will then present how to adapt the Continuous Integration paradigms to hardware design and verification in order to minimize the integration feedback loop, increase status visibility while still keeping a coverage driven verification, requirement based verification and assertion based verification approach in mind. This paper also illustrates how a Continuous Integration tool such as Jenkins can be used to enhance project visibility, based on the user experience of adopting this approach on to a couple of projects for the Space Industry and in the IoT domains.

DVCon India is a 2-day event attended by industry leaders, system architects, verification experts, SoC integrators, chip designers, IP developers, VIP developers and firmware engineers. The conference has onel track dedicated to Design & Verification languages, methodologies based on SystemVerilog, Verilog, UVM and technologies such as Formal Verification, Hardware Acceleration, Emulation and prototyping, along with the most widely used simulation and more.