The ST Verification School or how to solve the need for Verification engineers

The ST Verification School or how to solve the need for Verification engineers

[version française]

When thinking of microelectronics engineering, you may think hardware, firmware and maybe software development activities. You may not think, however, of verification engineers even if they are key elements in a team.

Verification engineers develop and implement testing procedures to determine if a product works as intended.  As the verification of complex FPGAs and ASICs is a crucial part of any project, specialised engineers with verification skills are essential.

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The lack of verification engineers, a headache for companies

Ten years ago, verification engineers were under-represented. Right now, their number has grown to the point where they are more numerous than design engineers on many projects. According to the Wilson Research Group Functional Verification Study (published by Harry Foster, in November 2020*) verification activities represent more than half of project time!

“Verification engineers are rare and desired profiles everywhere because they need to understand both hardware and software designs. On top of that, products are more and more complex and need a growing number of functional verification competences.” – Mirella Negro, MCD Verification Manager at ST and Verification School Sponsor

However, only a few engineering schools propose the discipline in their program. Companies are then seeing a skill shortage in this area and need to find solutions to train their employees.

On another hand, existing trainings only offer a quick overview of the verification languages and tools. 3 or 4 days to have the basis and then, employees have to learn methodologies by themselves and find out how to apply them in their own projects, leading to a very long learning curve before being efficient.

Given the complexity of the task, this is not a viable solution!

To solve this, STMicroelectronics has set up, in collaboration with its verification partners – AEDVICES Consulting, Cadence and ICONDA Solutions – a new, internal learning and development solution for functional verification, to enable software and designer engineers to acquire the knowledge and skills needed in this interesting and challenging area.

The ST Verification School is a 1-year program, including classrooms, workshops and tutoring for each student. A new way to teach, much more project-oriented, adaptative and agile.

The ST Verification School opened in May 2019 with a brand-new program and a dozen highly motivated international students. STMicroelectronics provided overall management and individual tutors for each student while AEDVICES Consulting looked after classroom and workshop content, Cadence supplied eLearning materials and ICONDA developed the Learning Objectives’ processes and measurement.

Together, AEDVICES Consulting and ICONDA supervised the overall learning process, ensuring that Learning Objectives were adapted as the program evolved (the number of adaptations was somewhat higher than expected, thanks to a certain virus!).

A great combination of different ways to learn

The first-year program is now complete and has been a success in both the program delivery, and more important the integration of new verification engineers in the teams. The program combines different ways to learn:

  • live courses for the most important theoretical content
  • workshops to go from theory to practice
  • independent learning through on-the-job projects and using eLearning, for example
  • tutoring with internal senior verification engineers and external experts
  • checkpoints as a finale activity, where students demonstrated their new expertise by defending their written work and presenting a case study.

To share some figures, students split their time with around 25% of Verification Theoretical training with workshop, 25% of tutoring by a dedicated tutor and with the verification community and 50% training on the job.

From the beginning, the delivery mechanisms for all these items were both classroom-based and remote, allowing students from geographically dispersed sites to attend the school. With the arrival of Covid-19, remote mechanisms became crucially important, of course.

The program was held together by a hierarchy of Learning Objectives, derived from an existing set of competence criteria that ST had defined for its verification engineers.

“The idea was to dispose of a toolbox and pick up in the box what was the most useful for students to acquire: mastery of UVM, competence in formal verification, verification methodologies, etc. Each component of the program – lectures, workshops, eLearning, etc. – was associated with set of Learning Objectives. According to this set of competences, we have created a fully agile and personalised technical content.”François Cerisier, CEO of AEDVICES Consulting

The students’ progress towards these objectives was measured regularly, using a self-assessment mechanism. Finally, the written part of the end-of-program checkpoint activity ensured that key Learning Objectives had indeed been met. This gave a sense of convergence not only to the program but also to each student’s learning experience.

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Verification School agility

“While we did not formalise an agile process for the development of the school’s first program (using SCRUM, for example) we certainly worked with an agile spirit. In particular, we started with a clear sense of direction, provided by the ST competence area definitions and our first set of Learning Objectives, as mentioned above. This allowed us to develop a schedule for the whole program and detailed content for the first quarter” Andrew Betts, CEO of ICONDA

At this point, the rubber hit the road. Students of the school are professionals, already working on specific projects and coming from various backgrounds, some hardware-oriented, others with more of a software flavour. Each of them has specific needs, priorities and preferences as far as methodology and tools were concerned. Some are preoccupied with UVM-related issues for block verification, for example, while others are drawn more towards system-level verification or formal methods. While ensuring that all students gained a certain mastery of a full range of verification strategies and techniques, AEDVICES Consulting and ICONDA had to constantly work with ST to adapt to emerging needs.

“At ST, a coreteam based of verification managers, training and human resource representatives was setup since the beginning. All together, we defined the expected professional competences, elaborating a program mixing courses made internally and externally. The progress was reviewed continuously taking any agile actions required to achieve the verification school goals. All this thanks to a “scrum” collaboration with AEDVICES Consulting and ICONDA” – Christophe Chevallaz, ST Verification School program leader

These reviews led to updates that were immediately integrated into the program. Feedback came directly from students (the Kirkpatrick measurement system was used) and also from workshops between the tutors and trainers. This ‘agile’ cycle was repeated about 4 times over the course of the program that corresponds to the 4 main steps : basic trainings, common core on simulation, common core on formal and advanced verification techniques.

A deep tutoring support

To improve the learning curve, each student had an individual tutor/mentor, providing encouragement, technical help and logistical assistance (e.g. for project scheduling). The tutors were themselves supervised by AEDVICES Consulting and ICONDA : in general, AEDVICES Consulting focused on the technical aspects while ICONDA gave support for management ones. Something not clear? A need to go deeper? Such questions were picked up by tutors and relayed to the AEDVICES Consulting and ICONDA facilitators who then responded either by helping tutors to help their tutees (a train the trainer approach) or by creating examples and exercises for inclusion in future classes or by giving individual support to students with a particular need.

What’s the next step?

The Verification School’s first set of graduates is now fully operational and working on ST verification projects. Furthermore, the school’s methodology and content have been verified and all its bugs have been found and fixed. Well, almost all of them J. Either way, we are looking forward to renewing the experience and bringing more verification engineers up to speed!

 

AEDVICES Consulting et ATP Formation lancent deux nouvelles formations sur Grenoble et Sophia-Antipolis

ATP Formation rend l’expertise d’AEDVICES en vérification fonctionnelle encore plus accessible aux entreprises avec, pour démarrer leur collaboration, de nouvelles offres en SystemC/TLM et SystemVerilog/UVM

Moirans, France – 18 Janvier 2019

Dans le cadre de ses activités de formation, AEDVICES Consulting s’associe à ATP Formation afin de vous proposer de nouvelles formations inter-entreprises sur Grenoble et Sophia-Antipolis sur deux thèmes de notre expertise :

  • Introduction à SystemC et Transaction Level Modeling (TLM), 20-23 Mars 2019 à Grenoble
  • UVM : Méthodologies de vérification pour IP et SoC, 25-28 Mars 2019 à Sophia Antipolis

Les Formations

Introduction à SystemC et Transaction Level Modeling (TLM)

A destination des Ingénieurs (HW et SW), architectes et chefs de projet concernés par la conception, l’étude, l’optimisation et la vérification des Ips et Systems on Chip, cette formation s’oriente sur l’apprentissage des approches et méthodologies de modélisations des “blocks” (Ips) et des “systèmes semi-conducteurs complexes” (System on Chip), ainsi que sur l’apprentissage et l’expérimentation avec SystemC, TLM/Virtual Prototyping à plusieurs niveaux d’abstraction.

Date : 20 au 23 Mars 2019 à Grenoble

Informations et réservation sur Atp Formation

UVM : Méthodologies de vérification pour IP et SoC

Cette formation s’adresse aux ingénieurs et chef de projet désirant acquérir des approches et méthodologies pour la vérification des “modules” (IPs) et de systèmes sur puce (System on Chip). Elle comprend l’utilisation du langage SystemVerilog et des librairies UVM (Universal Verification Methodology) pour la mise en œuvre de ces approches, la présentation des principaux composants en UVM ainsi que la création de tests aux deux niveaux (IP et SoC).

Date : du 25 au 28 Mars 2019 à Sophia Antipolis

Informations et réservation sur ATP Formation

À propos de ATP Formation

Atp Formation est une société de services spécialisée dans les formations informatiques. Que ce soit en bureautique, base de données, P.A.O, multimédia, C.A.O/D.A.O, gestion commerciale/paye/comptabilité, gestion de projets, internet/intranet, langages de programmation, systèmes d’exploitation/réseaux, elle déploie un large éventail de plus de 300 formations. Basée sur Meylan, Atp Formation propose des formations sur Meylan, Moirans et Sophia Antipolis.

Andrew Betts from ICONDA is joining AEDVICES Consulting

AEDVICES Consulting and ICONDA Solutions are coming together

AEDVICES Consulting, specialist in functional verification services, trainings and IP, is happy to welcome Andrew Betts as its new partner. He is joining our team to support functional verification sales and to strengthen our trainings catalogue.

Andrew is the owner of ICONDA Solutions and provides consulting, tranings and events for customer-facing teams.

This new collaboration is based on the reflexion that both activities are complementary. With AEDVICES Consulting’s expertise in functional verification and ICONDA’s expertise in many forms of trainings and facilitation, we hope to create a new synergy.

Launch of the Galactic Partner Program from Breker Verification Systems

With long term relationship with Breker, AEDVICES Consulting is proud to  be part of this this Galactic program to enable the adoption of the Portable Stimulus Standard.

Breker Verification Systems Forms Galactic Partner Program to Accelerate Portable Stimulus Standard Ecosystem

Inaugural Consulting and Training Partners Include AEDVICES Consulting, Axiomise, Sunburst Design, T&VS, Willamette HDL

SAN JOSE, CALIF. –– May 2, 2018 –– Breker Verification Systems, the leading provider of Portable Stimulus, today announced formation of its Galactic™ Partner Program, naming five inaugural consulting and training companies to help accelerate the Portable Stimulus Standard Ecosystem.

The inaugural partners are AEDVICES ConsultingAxiomiseSunburst DesignTest and Verification Solutions (T&VS) and Willamette HDL, all recognized verification experts who manage and support large chip design and verification projects. Under terms of the program, each will work to build the ecosystem around the upcoming Accellera Portable Stimulus Standard, a standard means of specifying verification intent and behaviors reusable across target platforms, using the Breker tool suite.

Specifically, Sunburst Design and Willamette HDL will become Portable Stimulus Standard trainers based on the Breker tool suite, while AEDVICES Consulting, Axiomise, and T&VS will offer verification consulting services also based on TrekSoC™ and TrekUVM™.

“As the Portable Stimulus Standard moves fully into the verification flow, it becomes critically important to have experts available to help further adoption,” states Adnan Hamid, Breker’s founder and chief executive officer. “We selected the best-known and regarded industry experts to train the users about the value and benefits of Portable Stimulus.”

Future announcements about Breker’s Galactic Partner Program will include new members who supply verification intellectual property (VIP) and tools. For more information about the Galactic Partner Program, visit: https://bit.ly/2GNUTNN

Breker first introduced a graph-based approach to test case generation in 2008, now known as Portable Stimulus. It gives chip design verification groups true Verification GPS (Graph-based, Portable, Shareable) with its Portable Stimulus solutions. Through the use of a Graph-based intent specification in an industry standard language, TrekSoC and TrekUVM offers proven Portability across verification platforms, scaling from IP to SoC for vertical reuse and SoC to post-silicon for horizontal reuse. It is Shareable across global diverse teams, project revisions and communication channels.

Breker’s tool suite is in use at large and mid-sized semiconductor companies worldwide on a variety of projects, including universal verification methodology (UVM) sequence synthesis and software-driven test generation from easy-to-author, graph-based representations and hardware/software scenario generation for emulation and system tests. Applications range from servers, networking, graphics processing units (GPUs) and field programmable gate arrays (FPGAs) to mobile and base stations for cellular wireless.
Breker is a founding member and an active participant of the Accellera Portable Stimulus Working Group (PSWG) and contributed a working C++ language representation for standardization efforts.

About Breker Verification Systems
Breker Verification Systems is the leading provider of Portable Stimulus solutions, a standard means to specify verification intent and behaviors reusable across target platforms, and the first company to introduce graph-based verification. Its Portable Stimulus suite of tools is Graph-based to make complex scenarios comprehensible, Portable, eliminating test redundancy across process, and Shareable to foster communication and reuse giving chip design verification groups true Verification GPS. Breker is privately held.

AEDVICES Consulting joins Mentor Graphics Questa Vanguard Program

 

AEDVICES Consulting joins Questa Vanguard Program, enabling high level verification services and expertise on Mentor Questa products, SystemVerilog, UVM, intelligent testbench.

The Questa Vanguard Program (QVP) extends Mentor Graphics’ breadth of design and verification technologies through partnerships with industry-leading companies. QVP partners provide verification related tools and methods, verification IP, conversion services, training and consulting based on Mentor Graphics industry leading Questa verification platform.  The program was established to bring design and verification engineers world-class product integrations and interoperability to enhance their Questa verification options and build a strong and comprehensive SystemVerilog ecosystem.