AEDVICES Consulting et ATP Formation lancent deux nouvelles formations sur Grenoble et Sophia-Antipolis

ATP Formation rend l’expertise d’AEDVICES en vérification fonctionnelle encore plus accessible aux entreprises avec, pour démarrer leur collaboration, de nouvelles offres en SystemC/TLM et SystemVerilog/UVM

Moirans, France – 18 Janvier 2019

Dans le cadre de ses activités de formation, AEDVICES Consulting s’associe à ATP Formation afin de vous proposer de nouvelles formations inter-entreprises sur Grenoble et Sophia-Antipolis sur deux thèmes de notre expertise :

  • Introduction à SystemC et Transaction Level Modeling (TLM), 20-23 Mars 2019 à Grenoble
  • UVM : Méthodologies de vérification pour IP et SoC, 25-28 Mars 2019 à Sophia Antipolis

Les Formations

Introduction à SystemC et Transaction Level Modeling (TLM)

A destination des Ingénieurs (HW et SW), architectes et chefs de projet concernés par la conception, l’étude, l’optimisation et la vérification des Ips et Systems on Chip, cette formation s’oriente sur l’apprentissage des approches et méthodologies de modélisations des “blocks” (Ips) et des “systèmes semi-conducteurs complexes” (System on Chip), ainsi que sur l’apprentissage et l’expérimentation avec SystemC, TLM/Virtual Prototyping à plusieurs niveaux d’abstraction.

Date : 20 au 23 Mars 2019 à Grenoble

Informations et réservation sur Atp Formation

UVM : Méthodologies de vérification pour IP et SoC

Cette formation s’adresse aux ingénieurs et chef de projet désirant acquérir des approches et méthodologies pour la vérification des “modules” (IPs) et de systèmes sur puce (System on Chip). Elle comprend l’utilisation du langage SystemVerilog et des librairies UVM (Universal Verification Methodology) pour la mise en œuvre de ces approches, la présentation des principaux composants en UVM ainsi que la création de tests aux deux niveaux (IP et SoC).

Date : du 25 au 28 Mars 2019 à Sophia Antipolis

Informations et réservation sur ATP Formation

À propos de ATP Formation

Atp Formation est une société de services spécialisée dans les formations informatiques. Que ce soit en bureautique, base de données, P.A.O, multimédia, C.A.O/D.A.O, gestion commerciale/paye/comptabilité, gestion de projets, internet/intranet, langages de programmation, systèmes d’exploitation/réseaux, elle déploie un large éventail de plus de 300 formations. Basée sur Meylan, Atp Formation propose des formations sur Meylan, Moirans et Sophia Antipolis.

Andrew Betts from ICONDA is joining AEDVICES Consulting

AEDVICES Consulting and ICONDA Solutions are coming together

AEDVICES Consulting, specialist in functional verification services, trainings and IP, is happy to welcome Andrew Betts as its new partner. He is joining our team to support functional verification sales and to strengthen our trainings catalogue.

Andrew is the owner of ICONDA Solutions and provides consulting, tranings and events for customer-facing teams.

This new collaboration is based on the reflexion that both activities are complementary. With AEDVICES Consulting’s expertise in functional verification and ICONDA’s expertise in many forms of trainings and facilitation, we hope to create a new synergy.

Launch of the Galactic Partner Program from Breker Verification Systems

With long term relationship with Breker, AEDVICES Consulting is proud to  be part of this this Galactic program to enable the adoption of the Portable Stimulus Standard.

Breker Verification Systems Forms Galactic Partner Program to Accelerate Portable Stimulus Standard Ecosystem

Inaugural Consulting and Training Partners Include AEDVICES Consulting, Axiomise, Sunburst Design, T&VS, Willamette HDL

SAN JOSE, CALIF. –– May 2, 2018 –– Breker Verification Systems, the leading provider of Portable Stimulus, today announced formation of its Galactic™ Partner Program, naming five inaugural consulting and training companies to help accelerate the Portable Stimulus Standard Ecosystem.

The inaugural partners are AEDVICES ConsultingAxiomiseSunburst DesignTest and Verification Solutions (T&VS) and Willamette HDL, all recognized verification experts who manage and support large chip design and verification projects. Under terms of the program, each will work to build the ecosystem around the upcoming Accellera Portable Stimulus Standard, a standard means of specifying verification intent and behaviors reusable across target platforms, using the Breker tool suite.

Specifically, Sunburst Design and Willamette HDL will become Portable Stimulus Standard trainers based on the Breker tool suite, while AEDVICES Consulting, Axiomise, and T&VS will offer verification consulting services also based on TrekSoC™ and TrekUVM™.

“As the Portable Stimulus Standard moves fully into the verification flow, it becomes critically important to have experts available to help further adoption,” states Adnan Hamid, Breker’s founder and chief executive officer. “We selected the best-known and regarded industry experts to train the users about the value and benefits of Portable Stimulus.”

Future announcements about Breker’s Galactic Partner Program will include new members who supply verification intellectual property (VIP) and tools. For more information about the Galactic Partner Program, visit:

Breker first introduced a graph-based approach to test case generation in 2008, now known as Portable Stimulus. It gives chip design verification groups true Verification GPS (Graph-based, Portable, Shareable) with its Portable Stimulus solutions. Through the use of a Graph-based intent specification in an industry standard language, TrekSoC and TrekUVM offers proven Portability across verification platforms, scaling from IP to SoC for vertical reuse and SoC to post-silicon for horizontal reuse. It is Shareable across global diverse teams, project revisions and communication channels.

Breker’s tool suite is in use at large and mid-sized semiconductor companies worldwide on a variety of projects, including universal verification methodology (UVM) sequence synthesis and software-driven test generation from easy-to-author, graph-based representations and hardware/software scenario generation for emulation and system tests. Applications range from servers, networking, graphics processing units (GPUs) and field programmable gate arrays (FPGAs) to mobile and base stations for cellular wireless.
Breker is a founding member and an active participant of the Accellera Portable Stimulus Working Group (PSWG) and contributed a working C++ language representation for standardization efforts.

About Breker Verification Systems
Breker Verification Systems is the leading provider of Portable Stimulus solutions, a standard means to specify verification intent and behaviors reusable across target platforms, and the first company to introduce graph-based verification. Its Portable Stimulus suite of tools is Graph-based to make complex scenarios comprehensible, Portable, eliminating test redundancy across process, and Shareable to foster communication and reuse giving chip design verification groups true Verification GPS. Breker is privately held.

AEDVICES Consulting joins Mentor Graphics Questa Vanguard Program


AEDVICES Consulting joins Questa Vanguard Program, enabling high level verification services and expertise on Mentor Questa products, SystemVerilog, UVM, intelligent testbench.

The Questa Vanguard Program (QVP) extends Mentor Graphics’ breadth of design and verification technologies through partnerships with industry-leading companies. QVP partners provide verification related tools and methods, verification IP, conversion services, training and consulting based on Mentor Graphics industry leading Questa verification platform.  The program was established to bring design and verification engineers world-class product integrations and interoperability to enhance their Questa verification options and build a strong and comprehensive SystemVerilog ecosystem.