Verification effort consumes over 55% of the IC Design effort and requires an increasing adoption of verification technologies within FPGA projects. Having the right functional verification approach which is depending on your project is now an essential.
With strong expertise in this domain, AEDVICES Consulting helps you define your verification approach, architect a proper verification environment and develop the appropriate test suite to hit your goals. Whether your project is driven by time to market, or by a formal requirement tracking process such as DO-254 and ISO26262, we can find the best approach to support your project.
Our expertise is based on 3 elements:
Requirement Based Verification
Assertion Based Verification
Scripting: Python, Perl, …
IP, Subsystems, CPU, DSP
Tool assessment and qualification
Delivery of a verification IP bundle and verification methodology training.
“eVaderis, a semiconductor IP company delivering innovative Non-Volatile solution for advanced subsystem, licensed AEDVICES verification IP for the development of its chips. We are pleased to use these highly qualified VIPs, which are frequently updated to track to norms evolutions. Thanks to AEDVICES training and excellent support, the VIPs have been easily integrated in eVaderis design flow.” Fabrice Bernard-Granger, Founder & COO
Member of Mentor Graphics Questa Vanguard Program we strongly follow the latest advances in stimuli generation, UVM and portable stimulus standards.
As a OneSpin Spinnaker member, we also follow the latest technology adoptions in formal verification, fault tolerant systems and theorem proving.
Our team can jump on your existing projects, or develop the entire verification process starting from the verification plan through to the verification closure.
 Wilson Research Group Functional Verification Study – 2016