Mentor User2User Conference : a great technical event

Aedvices Consulting's presentation at Mentor U2U Europe ConferenceMentor User2User Europe Conference – a one-day conference and exhibition dedicated to end-users of Mentor EDA solutions – was very successful. The presentations were of good quality and very interesting.

Francois Cerisier, Aedvices Consulting's CEOAs a Questa Vanguard program partner, Aedvices Consulting was invited to present during the event. In the SoC Verification track, Francois Cerisier presented “Applying Continuous Integration to Hardware Design & Verification” in front of a panel of verification engineers up to design managers in IoT, avionics or automotive. This has been well received and interesting questions were raised.

Good contacts were made during the breaks and the evening event. And it is always a pleasure to gather great technical discussions with industrials and other companies.

Presentation during U2U Europe

U2U Europe

The new Mentor User Conference, USer2User Europe (U2U Europe), will be held in Munich on November 27, 2017.


During this event, technical experts will present the latest advances in their domain. 

U2U Europe focuses on four key areas:

  • IC Design & Test
  • Functional Verification and Emulation
  • Analog Mixed-signal & Physical Verification
  • PCB Design & Analysis

François Cerisier, CEO of Aedvices Consulting, will present his paper “Applying Continuous Integration to Hardware Design and Verification” Track Functional Verification, Salon Cezanne, at 4:00pm

Take also the opportunity to meet us during the all day and the evening network event.

SAFE-Air 2017-2022 Project is looking for a PhD Student

Subject : Safety Evaluation of Aircraft Systems using Virtual Platforms

Confronted with increasingly stringent requirements for certification in operational safety, companies in the field of transport are looking for new methods to assess the robustness of complex digital integrated systems. In particular, our industrial partners in this project, THALES Valence and AEDVICES Consulting, are interested in the robustness of flight systems used in aeronautics. Integrated systems, due to the evolution of technologies, are increasingly sensitive to disturbances caused, for example, by atmospheric particles. Beyond aeronautical systems and transport systems in general (automotive, railway, etc.), the results of this project concern all the integrated systems used in critical applications: energy generation systems (nuclear power plant), medical implants…

The aim of the thesis is to propose a new approach to allow a more precise evaluation of the level of robustness of critical complex digital systems very early in development.

This project is part of the AURA (Auvergne Rhône Alpes) region’s “DIGITAL” and “MOBILITY, INTELLIGENT TRANSPORT SYSTEMS” areas of excellence. It is also part of the MINALOGIC competitiveness cluster.

The PhD student will be located within the LCIS laboratory in Valence (26). The thesis will be supervised by professors from three laboratories: LCIS, TIMA (Grenoble), and LHC (Saint Etienne).
How to Apply
Applicants must hold a Master (or equivalent) in Computer Science, Embedded System or Microelectronics.
Candidates must send a CV, a letter of motivation, details of the grades for each master courses and the classification in master years, and at least one letter of recommendation.

Details of the PhD Subject Safety Evaluation of Aircraft Systems using Virtual Platforms

VerifWorks and AEDVICES Consulting will present during DVCon India 2017

VerifWorks and Aedvices Consulting has collaborated to propose a paper during DVCon India 2017.

The paper “Adding Agility to Hardware Design-Verification using UVM & Assertions – with Jenkins for Continuous Integration” will be presented by Srujana Reddy on Friday, September 15 during the “DV Papers : Regression” Session (4:00pm to 5:30pm).

This paper presents the main differences between software development and hardware verification in terms of integration process, with an emphasis of the hardware development constraints which make the Continuous Integration flow not directly applicable.

It will then present how to adapt the Continuous Integration paradigms to hardware design and verification in order to minimize the integration feedback loop, increase status visibility while still keeping a coverage driven verification, requirement based verification and assertion based verification approach in mind. This paper also illustrates how a Continuous Integration tool such as Jenkins can be used to enhance project visibility, based on the user experience of adopting this approach on to a couple of projects for the Space Industry and in the IoT domains.

DVCon India is a 2-day event attended by industry leaders, system architects, verification experts, SoC integrators, chip designers, IP developers, VIP developers and firmware engineers. The conference has onel track dedicated to Design & Verification languages, methodologies based on SystemVerilog, Verilog, UVM and technologies such as Formal Verification, Hardware Acceleration, Emulation and prototyping, along with the most widely used simulation and more.

AEDVICES Consulting recrute un ingénieur en vérification hardware

Ingénieur consultant(e) en vérification, vous intervenez sur les projets clients en vérification fonctionnelle et mise en place des méthodologies et environnements de vérification. Vous serez aussi amené(e) à intervenir sur les développements internes (IP de vérification, flots, démonstrateur sur plateforme SoC/FPGA).

Encadré(e) par un expert en vérification et un expert en design/FPGA, vous serez, en fonction de votre profile, formé(e) et coaché(e) aux approches et méthodologies nécessaires à votre mission, pour ainsi évoluer vers une expertise technique à forte valeur ajoutée.

Poste basé à Moirans (38) -proche Grenoble-, vous êtes amené(e) à intervenir ponctuellement chez nos clients en France et en Europe.

De formation ingénieur ou équivalent, vous avez une sensibilité technique à la fois hardware et software.

Une première expérience ou un stage significatif en design ou en vérification vous permet d’appréhender les problèmes techniques d’un système sur puce ainsi que la compréhension de spécifications clients.

Compétences Clés

Maitrise des langages de conception VHDL et Verilog
Architecture des Systèmes FPGA et/ou System-On-Chip
Compréhension des protocoles de bus de communication SoC
Programmation Objet (C++ / Java ou autre)
Scripting (TCL, Perl, Python, …)
Compétences Additionnelles

Connaissances minimales en SystemVerilog
Connaissances des protocoles AMBA (AHB, APB, AXI), SPI, I2C, UART, Ethernet, USB, PCI, …
Programmation Software bas niveau, driver, RT-OS (assembleur, C)
Flots FPGA (Xilinx, Altera, MicroSemi, …)
Méthodologie de test et de vérification fonctionnelle

AEDVICES Consulting agréé en tant qu’organisme éligible au Crédit Impôt Recherche

CIR - Crédit Impôt RechercheAEDVICES Consulting est désormais agréé par le Ministère de l’enseignement supérieur, de la Recherche et de l’Innovation en tant qu’organisme exécutant des travaux de R&D pour le compte d’entreprises.


Qu’est-ce que cela signifie ?

Les entreprises peuvent faire appel à AEDVICES Consulting pour mener des travaux de R&D et ainsi bénéficier du crédit impôt recherche sur les opérations effectuées. Le crédit d’impôt recherche (CIR) est une aide publique qui permet de soutenir l’effort des entreprises en matière de R&D (recherche fondamentale, recherche appliquée, développement expérimental) et en matière d’innovation (dépenses de réalisation de prototypes ou installations pilotes de nouveaux produits).

Verification Horizons: Complex Signal Processing Verification Under DO-254 Constraints

Check out Verification Horizons, March 2016 and learn how to combine assertions and coverage for Complex Signal Processing Verification under DO-254 

from Mentor Graphics – Verification Horizons – Volume 12 – Issue 1

Building a complex signal processing function requires a deep understanding of the signal characteristics and of the different algorithms and their performances.

When it comes to the verification[a] of such designs, a quite generic approach consists of injecting more or less realistic stimulus and using a reference models (most often C or Matlab), to compare the expected results.

Requirement based designs following a DO 254[1] process add the constraints that each function of the design should be specified as a traceable requirement.  The proof of the complete verification of each requirement should also be provided with additional emphasis on physical verification, therefore running the tests on the physical device.

This article describes a combined requirement and metric driven methodology developed at a customer site for the verification of a complex signal processing SoC block under DO 254 constraints. This methodology also enables both horizontal and vertical reuse of the tests, allowing tests to run both in both IP simulation and on FPGA boards at SoC level. This approach is described in a generic way and can be applied to different signal or data processing designs.

Full article in pdf