Adrien Carmagnat of AEDVICES on Functional Safety at DVCon Europe
Adrien Carmagnat, AEDVICES’ latest recruit and an expert in verification methodologies, presented a paper on Keeping up with rapidly advancing safety standards at DVCon Europe in Munich last month (2018 Proceedings will be made available late January on the DVCon website).
We were particularly pleased to present this work since (we believe) it makes a significant contribution to industry discussions on safety standards, and especially the part that Functional Verification has to play.
Furthermore, it is the fruition of an excellent collaboration with our customer, Melexis, and it’s been a great professional development experience for Adrien.
Adrien started as a trainee within AEDVICES Consulting eight months ago having majored in Embedded Systems at Polytech’Sophia. He has been trained on Advanced Verification Methodologies and during his internship he also developed skills in Verification IP and Tool Qualification. To recognise his excellent contribution to the project, we asked Adrien to step up to the plate and make the DVCon presentation, knowing there was a lot of verification expertise in the audience and that this would be a challenge!
Adrien was proud to make the presentation (and a bit nervous, too!). As he said afterwards: “I went on stage with a bit of stress, but it turned out to be easier than I’d expected! The attendees seemed interested. They asked probing questions and even shared some ideas that are prompting me to dig deeper into the subject. They may be useful for another paper next year – who knows! “
AEDVICES Consulting and ICONDA Solutions are coming together
AEDVICES Consulting, specialist in functional verification services, trainings and IP, is happy to welcome Andrew Betts as its new partner. He is joining our team to support functional verification sales and to strengthen our trainings catalogue.
Andrew is the owner of ICONDA Solutions and provides consulting, tranings and events for customer-facing teams.
This new collaboration is based on the reflexion that both activities are complementary. With AEDVICES Consulting’s expertise in functional verification and ICONDA’s expertise in many forms of trainings and facilitation, we hope to create a new synergy.
Adrien CARMAGNAT and François CERISIER, will present their paper during the new edition of DVCon Europe.
The Design and Verification Conference (DVCon) Europe is the leading European event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. This year, DVCon Europe will be held in Munich from October 24 to October 25.
To attend AEDVICES’ presentation:
“Qualification of a Verification IP under Requirement based Verification standards: An Approach to the Verification of the Verification” Thursday October 25, 3:15pm – 4:45pm | Forum 5 Functional Safety Session
AEDVICES Consulting has decided to change its logo and its visual identity to stay modern and actual.
In the same time, you will discover our new website. It is designed to help you find all relevant information about the company: our activities, our partners and our team. We will keep it updated with every news concerning our actuality.
Subject : Safety Evaluation of Aircraft Systems using Virtual Platforms
Confronted with increasingly stringent requirements for certification in operational safety, companies in the field of transport are looking for new methods to assess the robustness of complex digital integrated systems. In particular, our industrial partners in this project, THALES Valence and AEDVICES Consulting, are interested in the robustness of flight systems used in aeronautics. Integrated systems, due to the evolution of technologies, are increasingly sensitive to disturbances caused, for example, by atmospheric particles. Beyond aeronautical systems and transport systems in general (automotive, railway, etc.), the results of this project concern all the integrated systems used in critical applications: energy generation systems (nuclear power plant), medical implants…
The aim of the thesis is to propose a new approach to allow a more precise evaluation of the level of robustness of critical complex digital systems very early in development.
This project is part of the AURA (Auvergne Rhône Alpes) region’s “DIGITAL” and “MOBILITY, INTELLIGENT TRANSPORT SYSTEMS” areas of excellence. It is also part of the MINALOGIC competitiveness cluster.
The PhD student will be located within the LCIS laboratory in Valence (26). The thesis will be supervised by professors from three laboratories: LCIS, TIMA (Grenoble), and LHC (Saint Etienne).
How to Apply
Applicants must hold a Master (or equivalent) in Computer Science, Embedded System or Microelectronics.
Candidates must send a CV, a letter of motivation, details of the grades for each master courses and the classification in master years, and at least one letter of recommendation.
VerifWorks and Aedvices Consulting has collaborated to propose a paper during DVCon India 2017.
The paper “Adding Agility to Hardware Design-Verification using UVM & Assertions – with Jenkins for Continuous Integration” will be presented by Srujana Reddy on Friday, September 15 during the “DV Papers : Regression” Session (4:00pm to 5:30pm).
This paper presents the main differences between software development and hardware verification in terms of integration process, with an emphasis of the hardware development constraints which make the Continuous Integration flow not directly applicable.
It will then present how to adapt the Continuous Integration paradigms to hardware design and verification in order to minimize the integration feedback loop, increase status visibility while still keeping a coverage driven verification, requirement based verification and assertion based verification approach in mind. This paper also illustrates how a Continuous Integration tool such as Jenkins can be used to enhance project visibility, based on the user experience of adopting this approach on to a couple of projects for the Space Industry and in the IoT domains.
DVCon India is a 2-day event attended by industry leaders, system architects, verification experts, SoC integrators, chip designers, IP developers, VIP developers and firmware engineers. The conference has onel track dedicated to Design & Verification languages, methodologies based on SystemVerilog, Verilog, UVM and technologies such as Formal Verification, Hardware Acceleration, Emulation and prototyping, along with the most widely used simulation and more.