Our Expertise

Expertise in consulting
CONSULTING

AEDVICES Consulting provides EDA, Semiconductors and Embedded Systems companies with project support, application engineering, design development and verification services and tools.

Expertise in Verification IP
VERIFICATION IP

AEDVICES Consulting develops and provides quality verification IPs (VIP). Designed with full debug, full functional coverage and full protocol checkers, our VIPs will leverage your verification tasks and speed up your verification process.

Expertise in Verification Methodology trainings
TRAININGS

Strengthened through experience on IP and SoC verification projects, AEDVICES Consulting proposes trainings in verification methodologies. Labs use a unique dual-core SoC platform to illustrate the main concepts both at IP and SoC levels.

Partners and Projects

AEDVICES Consulting is Member of
Galactic Partner Program
Questa Vanguard Program
Spinnaker Program
Examples of projects:

Specification, development, verification and realization of the digital control block.

“IRLYNX develops infrared modules to detect and characterize human activity. Its sensors, low-cost and respecting users’ privacy deliver in real-time advanced data about true presence in a room, people counting, their location and trajectories. Many thanks to AEDVICES and its close co-operation with IRLYNX to develop digital parts of our chip in a very flexible and professional way!” Sébastien Fabre, CEO

Delivery of a verification IP bundle and verification methodology training.

“eVaderis, a semiconductor IP company delivering innovative Non-Volatile solution for advanced subsystem, licensed AEDVICES verification IP for the development of its chips. We are pleased to use these highly qualified VIPs, which are frequently updated to track to norms evolutions. Thanks to AEDVICES training and excellent support, the VIPs have been easily integrated in eVaderis design flow.” Fabrice Bernard-Granger, Founder & COO

Regional Project:

SAFE-Air, in collaboration with ESISAR, TIMA and Thales

Lectures:

AEDVICES Consulting is engaged alongside Polytech’nice and ESISAR to give verification lectures

        

News

Intervention de François Cerisier lors de la FPGA Verification Conference de CadLog

Saviez-vous que « que 80% des conceptions de FPGA critiques pour la sécurité contiennent des bugs non triviaux qui ne sont pas détectés pendant la production » (Etude du Wilson Research Group) ? Pour tous ceux qui s’interrogent sur « Comment atteindre le niveau de sécurité fonctionnelle requis pour une conception FPGA », venez assister gratuitement à la FPGA Verification …

Jean-Marc Tribaudot joins AEDVICES Consulting as COO

Thanks to the arrival of Jean-Marc, the company will be able to strengthen its competencies in ASIC design, extend its customer portfolio and broaden its network of technical experts. Francois Cerisier and Jean-Marc Tribaudot, AEDVICES Consulting Prior to joining AEDVICES Consulting, Jean-Marc Tribaudot has been a freelance digital design consultant for several years and has …

AEDVICES Consulting et ATP Formation lancent deux nouvelles formations sur Grenoble et Sophia-Antipolis

ATP Formation rend l’expertise d’AEDVICES en vérification fonctionnelle encore plus accessible aux entreprises avec, pour démarrer leur collaboration, de nouvelles offres en SystemC/TLM et SystemVerilog/UVM Moirans, France – 18 Janvier 2019 Dans le cadre de ses activités de formation, AEDVICES Consulting s’associe à ATP Formation afin de vous proposer de nouvelles formations inter-entreprises sur Grenoble …