Our Expertise

Expertise in consulting

AEDVICES Consulting provides EDA, Semiconductors and Embedded Systems companies with project support, application engineering, design development and verification services and tools.

Expertise in Verification IP

AEDVICES Consulting develops and provides quality verification IPs (VIP). Designed with full debug, full functional coverage and full protocol checkers, our VIPs will leverage your verification tasks and speed up your verification process.

Expertise in Verification Methodology trainings

Strengthened through experience on IP and SoC verification projects, AEDVICES Consulting proposes trainings in verification methodologies. Labs use a unique dual-core SoC platform to illustrate the main concepts both at IP and SoC levels.

Partners and Projects

AEDVICES Consulting is Member of
Galactic Partner Program
Questa Vanguard Program
Spinnaker Program
Examples of projects:

Specification, development, verification and realization of the digital control block.

“IRLYNX develops infrared modules to detect and characterize human activity. Its sensors, low-cost and respecting users’ privacy deliver in real-time advanced data about true presence in a room, people counting, their location and trajectories. Many thanks to AEDVICES and its close co-operation with IRLYNX to develop digital parts of our chip in a very flexible and professional way!” Sébastien Fabre, CEO

Delivery of a verification IP bundle and verification methodology training.

“eVaderis, a semiconductor IP company delivering innovative Non-Volatile solution for advanced subsystem, licensed AEDVICES verification IP for the development of its chips. We are pleased to use these highly qualified VIPs, which are frequently updated to track to norms evolutions. Thanks to AEDVICES training and excellent support, the VIPs have been easily integrated in eVaderis design flow.” Fabrice Bernard-Granger, Founder & COO

Regional Project:

SAFE-Air, in collaboration with ESISAR, TIMA and Thales


AEDVICES Consulting is engaged alongside Polytech’nice and ESISAR to give verification lectures



Bienvenue à Guillaume, nouvel embauché au sein d’AEDVICES Consulting !

Guillaume a fait son stage de fin d’étude chez AEDVICES. Désormais diplômé, il nous rejoint en tant qu’ingénieur vérification junior. Petite présentation de notre nouveau membre… Peux-tu te présenter en quelques mots ? Je m’appelle Guillaume. J’ai fait mes études à PHELMA où j’ai également pu bénéficier d’un programme d’échange avec l’Ecole Polytechnique Fédérale de Lausanne …

Intervention de François Cerisier lors de la FPGA Verification Conference de CadLog

Saviez-vous que « que 80% des conceptions de FPGA critiques pour la sécurité contiennent des bugs non triviaux qui ne sont pas détectés pendant la production » (Etude du Wilson Research Group) ? Pour tous ceux qui s’interrogent sur « Comment atteindre le niveau de sécurité fonctionnelle requis pour une conception FPGA », venez assister gratuitement à la FPGA Verification …