Adrien CARMAGNAT and François CERISIER, will present their paper during the new edition of DVCon Europe.
The Design and Verification Conference (DVCon) Europe is the leading European event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. This year, DVCon Europe will be held in Munich from October 24 to October 25.
To attend AEDVICES’ presentation:
“Qualification of a Verification IP under Requirement based Verification standards: An Approach to the Verification of the Verification”
Thursday October 25, 3:15pm – 4:45pm | Forum 5
Functional Safety Session
More information and registration : DVCon Europe website
Mentor User2User Europe Conference – a one-day conference and exhibition dedicated to end-users of Mentor EDA solutions – was very successful. The presentations were of good quality and very interesting.
As a Questa Vanguard program partner, Aedvices Consulting was invited to present during the event. In the SoC Verification track, Francois Cerisier presented “Applying Continuous Integration to Hardware Design & Verification” in front of a panel of verification engineers up to design managers in IoT, avionics or automotive. This has been well received and interesting questions were raised.
Good contacts were made during the breaks and the evening event. And it is always a pleasure to gather great technical discussions with industrials and other companies.
The new Mentor User Conference, USer2User Europe (U2U Europe), will be held in Munich on November 27, 2017.
During this event, technical experts will present the latest advances in their domain.
U2U Europe focuses on four key areas:
- IC Design & Test
- Functional Verification and Emulation
- Analog Mixed-signal & Physical Verification
- PCB Design & Analysis
François Cerisier, CEO of Aedvices Consulting, will present his paper “Applying Continuous Integration to Hardware Design and Verification” Track Functional Verification, Salon Cezanne, at 4:00pm
Take also the opportunity to meet us during the all day and the evening network event.
VerifWorks and Aedvices Consulting has collaborated to propose a paper during DVCon India 2017.
The paper “Adding Agility to Hardware Design-Verification using UVM & Assertions – with Jenkins for Continuous Integration” will be presented by Srujana Reddy on Friday, September 15 during the “DV Papers : Regression” Session (4:00pm to 5:30pm).
This paper presents the main differences between software development and hardware verification in terms of integration process, with an emphasis of the hardware development constraints which make the Continuous Integration flow not directly applicable.
It will then present how to adapt the Continuous Integration paradigms to hardware design and verification in order to minimize the integration feedback loop, increase status visibility while still keeping a coverage driven verification, requirement based verification and assertion based verification approach in mind. This paper also illustrates how a Continuous Integration tool such as Jenkins can be used to enhance project visibility, based on the user experience of adopting this approach on to a couple of projects for the Space Industry and in the IoT domains.
DVCon India is a 2-day event attended by industry leaders, system architects, verification experts, SoC integrators, chip designers, IP developers, VIP developers and firmware engineers. The conference has onel track dedicated to Design & Verification languages, methodologies based on SystemVerilog, Verilog, UVM and technologies such as Formal Verification, Hardware Acceleration, Emulation and prototyping, along with the most widely used simulation and more.
Check out Verification Horizons, March 2016 and learn how to combine assertions and coverage for Complex Signal Processing Verification under DO-254
from Mentor Graphics – Verification Horizons – Volume 12 – Issue 1
Building a complex signal processing function requires a deep understanding of the signal characteristics and of the different algorithms and their performances.
When it comes to the verification[a] of such designs, a quite generic approach consists of injecting more or less realistic stimulus and using a reference models (most often C or Matlab), to compare the expected results.
Requirement based designs following a DO 254 process add the constraints that each function of the design should be specified as a traceable requirement. The proof of the complete verification of each requirement should also be provided with additional emphasis on physical verification, therefore running the tests on the physical device.
This article describes a combined requirement and metric driven methodology developed at a customer site for the verification of a complex signal processing SoC block under DO 254 constraints. This methodology also enables both horizontal and vertical reuse of the tests, allowing tests to run both in both IP simulation and on FPGA boards at SoC level. This approach is described in a generic way and can be applied to different signal or data processing designs.
Full article in pdf