The ST Verification School or how to solve the need for Verification engineers

[version française]

When thinking of microelectronics engineering, you may think hardware, firmware and maybe software development activities. You may not think, however, of verification engineers even if they are key elements in a team.

Verification engineers develop and implement testing procedures to determine if a product works as intended.  As the verification of complex FPGAs and ASICs is a crucial part of any project, specialised engineers with verification skills are essential.

Hand writing Mentoring crossword concept with marker on transparent wipe board isolated on white.

The lack of verification engineers, a headache for companies

Ten years ago, verification engineers were under-represented. Right now, their number has grown to the point where they are more numerous than design engineers on many projects. According to the Wilson Research Group Functional Verification Study (published by Harry Foster, in November 2020*) verification activities represent more than half of project time!

“Verification engineers are rare and desired profiles everywhere because they need to understand both hardware and software designs. On top of that, products are more and more complex and need a growing number of functional verification competences.” – Mirella Negro, MCD Verification Manager at ST and Verification School Sponsor

However, only a few engineering schools propose the discipline in their program. Companies are then seeing a skill shortage in this area and need to find solutions to train their employees.

On another hand, existing trainings only offer a quick overview of the verification languages and tools. 3 or 4 days to have the basis and then, employees have to learn methodologies by themselves and find out how to apply them in their own projects, leading to a very long learning curve before being efficient.

Given the complexity of the task, this is not a viable solution!

To solve this, STMicroelectronics has set up, in collaboration with its verification partners – AEDVICES Consulting, Cadence and ICONDA Solutions – a new, internal learning and development solution for functional verification, to enable software and designer engineers to acquire the knowledge and skills needed in this interesting and challenging area.

The ST Verification School is a 1-year program, including classrooms, workshops and tutoring for each student. A new way to teach, much more project-oriented, adaptative and agile.

The ST Verification School opened in May 2019 with a brand-new program and a dozen highly motivated international students. STMicroelectronics provided overall management and individual tutors for each student while AEDVICES Consulting looked after classroom and workshop content, Cadence supplied eLearning materials and ICONDA developed the Learning Objectives’ processes and measurement.

Together, AEDVICES Consulting and ICONDA supervised the overall learning process, ensuring that Learning Objectives were adapted as the program evolved (the number of adaptations was somewhat higher than expected, thanks to a certain virus!).

A great combination of different ways to learn

The first-year program is now complete and has been a success in both the program delivery, and more important the integration of new verification engineers in the teams. The program combines different ways to learn:

  • live courses for the most important theoretical content
  • workshops to go from theory to practice
  • independent learning through on-the-job projects and using eLearning, for example
  • tutoring with internal senior verification engineers and external experts
  • checkpoints as a finale activity, where students demonstrated their new expertise by defending their written work and presenting a case study.

To share some figures, students split their time with around 25% of Verification Theoretical training with workshop, 25% of tutoring by a dedicated tutor and with the verification community and 50% training on the job.

From the beginning, the delivery mechanisms for all these items were both classroom-based and remote, allowing students from geographically dispersed sites to attend the school. With the arrival of Covid-19, remote mechanisms became crucially important, of course.

The program was held together by a hierarchy of Learning Objectives, derived from an existing set of competence criteria that ST had defined for its verification engineers.

“The idea was to dispose of a toolbox and pick up in the box what was the most useful for students to acquire: mastery of UVM, competence in formal verification, verification methodologies, etc. Each component of the program – lectures, workshops, eLearning, etc. – was associated with set of Learning Objectives. According to this set of competences, we have created a fully agile and personalised technical content.”François Cerisier, CEO of AEDVICES Consulting

The students’ progress towards these objectives was measured regularly, using a self-assessment mechanism. Finally, the written part of the end-of-program checkpoint activity ensured that key Learning Objectives had indeed been met. This gave a sense of convergence not only to the program but also to each student’s learning experience.

Group of paper plane in one direction and with one individual pointing in the different way, can be used leadership/individuality concepts.( 3d render )

Verification School agility

“While we did not formalise an agile process for the development of the school’s first program (using SCRUM, for example) we certainly worked with an agile spirit. In particular, we started with a clear sense of direction, provided by the ST competence area definitions and our first set of Learning Objectives, as mentioned above. This allowed us to develop a schedule for the whole program and detailed content for the first quarter” Andrew Betts, CEO of ICONDA

At this point, the rubber hit the road. Students of the school are professionals, already working on specific projects and coming from various backgrounds, some hardware-oriented, others with more of a software flavour. Each of them has specific needs, priorities and preferences as far as methodology and tools were concerned. Some are preoccupied with UVM-related issues for block verification, for example, while others are drawn more towards system-level verification or formal methods. While ensuring that all students gained a certain mastery of a full range of verification strategies and techniques, AEDVICES Consulting and ICONDA had to constantly work with ST to adapt to emerging needs.

“At ST, a coreteam based of verification managers, training and human resource representatives was setup since the beginning. All together, we defined the expected professional competences, elaborating a program mixing courses made internally and externally. The progress was reviewed continuously taking any agile actions required to achieve the verification school goals. All this thanks to a “scrum” collaboration with AEDVICES Consulting and ICONDA” – Christophe Chevallaz, ST Verification School program leader

These reviews led to updates that were immediately integrated into the program. Feedback came directly from students (the Kirkpatrick measurement system was used) and also from workshops between the tutors and trainers. This ‘agile’ cycle was repeated about 4 times over the course of the program that corresponds to the 4 main steps : basic trainings, common core on simulation, common core on formal and advanced verification techniques.

A deep tutoring support

To improve the learning curve, each student had an individual tutor/mentor, providing encouragement, technical help and logistical assistance (e.g. for project scheduling). The tutors were themselves supervised by AEDVICES Consulting and ICONDA : in general, AEDVICES Consulting focused on the technical aspects while ICONDA gave support for management ones. Something not clear? A need to go deeper? Such questions were picked up by tutors and relayed to the AEDVICES Consulting and ICONDA facilitators who then responded either by helping tutors to help their tutees (a train the trainer approach) or by creating examples and exercises for inclusion in future classes or by giving individual support to students with a particular need.

What’s the next step?

The Verification School’s first set of graduates is now fully operational and working on ST verification projects. Furthermore, the school’s methodology and content have been verified and all its bugs have been found and fixed. Well, almost all of them J. Either way, we are looking forward to renewing the experience and bringing more verification engineers up to speed!


Happy Birthday Stéphanie !

Quand on vous parle d’une société de consulting en vérification et design, vous pensez tout de suite ingénieurs. Et pourtant, il faut toute une équipe solide pour gérer ces hommes et ces femmes au quotidien.

Depuis un an, c’est Stéphanie qui s’occupe de nous : gestion administrative, gestion RH et maintenant gestion Covid ! Et avec une équipe qui grossit régulièrement depuis son arrivée (nous sommes maintenant 16 employés + 4 prestataires), elle n’a pas le temps de s’ennuyer 😊

Alors comment perçoit-elle son travail et la société ? Comment sa personnalité la rend-elle unique à nos yeux ? Petite interview, sans langue de bois ni chichis.


Comment décrirais-tu ta journée de travail à un enfant ?

Je fais beaucoup de choses différentes dans la journée mais on peut dire que je m’occupe surtout de faciliter le travail des gens. Pour ça, je prépare les dossiers, gère les agendas et je m’assure que tout le monde se sente bien à son poste.

En trois mots, quel est ton rôle dans la société ?

Un peu plus de trois, ça passe ? Les deux choses qui définissent pour moi mon rôle : couteau suisse et faire du lien !

Quels sont tes principaux défis professionnels ?

Actuellement, il y a deux gros défis :

  • gérer la croissance de l’équipe tout en gardant un lien avec chaque membre de la société
  • être présente et disponible sur chaque aspect de mon poste (RH, admin, commercial, finances…)

Si tu devais changer une chose à propos de ton travail, qu’est-ce que ce serait ?

Depuis que je suis arrivée, nous avons beaucoup travaillé à la numérisation des documents et la mise en place d’outils d’optimisation des process. Mais malgré cela, il reste une bête noire pour moi : Excel 😊 Je ne peux malheureusement pas m’en passer complétement et j’avoue qu’Excel et moi, ça fait deux !

Qu’est-ce que tu préfères dans ton travail ?

J’adore la polyvalence de mon poste. Pas le temps de m’ennuyer (impossible pour moi d’être dans l’ennui), il y a toujours de nouvelles choses à faire. J’aime aussi l’idée de participer au développement de l’entreprise. Même si je ne fais pas partie des équipes techniques, j’apporte ma pierre à l’édifice. Et l’esprit humain et respectueux de cette entreprise, est primordial pour moi. J’ai besoin de m’y sentir bien pour faire mon travail sereinement.

Quels conseils aux nouvelles recrues ?

Les valeurs de l’entreprise (travail d’équipe, excellence technique, agilité) sont très présentes dans la société. Et cela s’est encore plus ressenti lors du confinement où la direction a mis tout en œuvre pour garder un lien avec chacun de nous (réunions virtuelles, formations techniques, enquête de satisfaction…). Donc si je vais donner un conseil, c’est de profiter de l’expertise des uns et des autres et ne pas hésiter à demander du support au démarrage. Les experts techniques sont au rendez-vous !

Quelle est la dernière fois où tu as ri aux larmes ?

Difficile à dire car je suis quelqu’un qui rigole très facilement. J’aime partager de bons moments entre amis, mais également entre collègues. Et puis rire c’est éclairer son quotidien mais également communiquer et se comprendre !

Si tu pouvais être quelqu’un d’autre le temps d’une journée, qui aimerais-tu être ?

Si j’avais une baguette magique de fée (et donc être une fée 😊), j’aimerais pouvoir réaliser un vœu pour chaque personne. C’est mon côté optimiste et bienveillante.

Si tu étais un personnage des Monsieur/Madame, lequel serais-tu ?

Je crois que je serais un mélange de Madame bavarde, Madame coquette et Madame câlin. Certainement d’autres aussi mais ce sont celles qui me plaisent le plus. Je pourrai également inventer Madame dynamique ou Madame tennis !

Le job le plus improbable que tu as fait avant de rejoindre la société ?

Pendant deux ans, j’ai pratiqué la médecine chinoise, je suis certifiée dans ce domaine ! C’était une expérience très riche et altruiste. Je garde également de ce statut d’auto-entrepreneure la compréhension des démarches administratives liées à la société mais également la dynamique d’entreprendre. J’en profite aussi pour transmettre des conseils en gestion du stress aux employés qui en ont besoin 😊.

Bienvenue à Guillaume, nouvel embauché au sein d’AEDVICES Consulting !

Guillaume a fait son stage de fin d’étude chez AEDVICES. Désormais diplômé, il nous rejoint en tant qu’ingénieur vérification junior. Petite présentation de notre nouveau membre…

Peux-tu te présenter en quelques mots ?

Je m’appelle Guillaume. J’ai fait mes études à PHELMA où j’ai également pu bénéficier d’un programme d’échange avec l’Ecole Polytechnique Fédérale de Lausanne (EPFL). Je suis passionné de vélo. Mon col préféré est au pied du Rocher de Lorzier, sommet de Chartreuse s’élevant à 1838m (et qui est aussi le nom de la rue de nos locaux !)

Guillaume Rollin, nouvel embauché Aedvices
Guillaume dans nos locaux (Août 2020)

Quel était le sujet de ton stage ?

Lors de mon stage, j’ai travaillé sur un projet interne de plateforme de démonstration basée sur la plateforme PULP à base de RiscV. Celle-ci est utilisée lors des formations que dispensent AEDVICES.

Cette plateforme permet à la fois de mettre en avant les dernières approches de vérification IP et SoC lors des trainings et d’avoir des démonstrateurs de briques de technologies disponibles pour résoudre les problèmes complexes couramment rencontré sur les projets.

Pour moi, travailler sur ce projet m’a permis de développer des compétences en design et également en vérification. Comme nombre d’étudiants en école d’ingénieur, je n’ai eu lors de mon cursus qu’une approche très superficielle de la vérification et ce stage m’a fait découvrir toutes les étendues possibles de cette activité.

Ton avis sur le suivi ?

Malgré la crise du covid-19, j’ai bénéficié d’un accompagnement quotidien. Lors du confinement, mon tuteur, François Cerisier, m’appelait tous les matins pour faire un point. Comparé à mes camarades de promo, j’ai vraiment été très bien encadré !

De plus, François Cerisier, a mis en place des trainings à distance pour les employés pendant le mois d’avril. J’ai pu assister à ces trainings et ainsi me perfectionner sur les méthodologies et les outils de vérification.

Depuis le retour dans les locaux d’AEDVICES, on continue nos réunions journalières, dans le respect des règles sanitaires.

Et l’équipe ?

Je n’ai pas eu l’occasion de bien côtoyer tout le monde à cause de la mise en place du télétravail mais nous avons un système de tchat via Teams. Ça permet de garder un lien malgré la distance physique des équipes.

Chaque employé possède une expertise soit en design, soit en vérification et est prêt à partager ses connaissances afin de faire progresser les autres et résoudre les problèmes des clients. C’est très appréciable de sentir qu’on peut compter les uns sur les autres et qu’il n’y a pas de rivalité.

Quelles vont être tes activités en tant que jeune embauché ?

A peine le stage terminé, j’ai commencé une mission auprès de mon premier client ! Malgré les conditions actuelles, l’équipe dirigeante d’AEDVICES reste en lien permanent avec ses employés, qu’ils soient sur site client, en télétravail ou dans nos locaux. C’est important d’avoir cette cohésion d’équipe quel que soit le lieu où l’on travaille.


Si vous êtes intéressé(e) pour nous rejoindre, AEDVICES accueille chaque année des stagiaires et recrute régulièrement des ingénieurs, débutants ou experts. Envoyez-nous votre candidature ici, nous serons ravis d’en discuter avec vous.


Intervention de François Cerisier lors de la FPGA Verification Conference de CadLog

Saviez-vous que « que 80% des conceptions de FPGA critiques pour la sécurité contiennent des bugs non triviaux qui ne sont pas détectés pendant la production » (Etude du Wilson Research Group) ? Pour tous ceux qui s’interrogent sur « Comment atteindre le niveau de sécurité fonctionnelle requis pour une conception FPGA », venez assister gratuitement à la FPGA Verification Conference 2019 organisée par CadLog, le 5 novembre à Roissy Charles de Gaulle.

Les interventions de Stefan Bauer, François Cerisier et Rachid Laaris, vous permettront d’appréhender les enjeux de la vérification FPGA. Ce sera également l’occasion de rencontrer des spécialistes de la vérification et d’échanger sur vos problématiques.

Inscrivez-vous maintenant !

Jean-Marc Tribaudot joins AEDVICES Consulting as COO

Thanks to the arrival of Jean-Marc, the company will be able to strengthen its competencies in ASIC design, extend its customer portfolio and broaden its network of technical experts.

Francois Cerisier and Jean-Marc Tribaudot, AEDVICES Consulting

Prior to joining AEDVICES Consulting, Jean-Marc Tribaudot has been a freelance digital design consultant for several years and has held technical and management positions at ST Microelectronics and Texas Instruments.

François Cerisier, CEO of AEDVICES Consulting, commented: “Getting Jean-Marc on board opens a new era for AEDVICES. We are now accelerating our recruitments to broaden our offering in both design and verification and take bigger projects from Spec to GDS.»

Jean-Marc Tribaudot said: “François has been a trusted partner for a long time, and I am very happy to join forces with him. Our complementarity will allow AEDVICES to grow faster and provide a complete response to our customers’ needs.”

The company plans to hire 10 engineers in the next few months, ranging from junior positions to technical experts.

AEDVICES Consulting et ATP Formation lancent deux nouvelles formations sur Grenoble et Sophia-Antipolis

ATP Formation rend l’expertise d’AEDVICES en vérification fonctionnelle encore plus accessible aux entreprises avec, pour démarrer leur collaboration, de nouvelles offres en SystemC/TLM et SystemVerilog/UVM

Moirans, France – 18 Janvier 2019

Dans le cadre de ses activités de formation, AEDVICES Consulting s’associe à ATP Formation afin de vous proposer de nouvelles formations inter-entreprises sur Grenoble et Sophia-Antipolis sur deux thèmes de notre expertise :

  • Introduction à SystemC et Transaction Level Modeling (TLM), 20-23 Mars 2019 à Grenoble
  • UVM : Méthodologies de vérification pour IP et SoC, 25-28 Mars 2019 à Sophia Antipolis

Les Formations

Introduction à SystemC et Transaction Level Modeling (TLM)

destination des Ingénieurs (HW et SW), architectes et chefs de projet concernés
par la conception, l’étude, l’optimisation et la vérification des Ips et
Systems on Chip, cette formation s’oriente sur l’apprentissage des approches et
méthodologies de modélisations des “blocks” (Ips) et des
“systèmes semi-conducteurs complexes” (System on Chip), ainsi que sur
l’apprentissage et l’expérimentation avec SystemC, TLM/Virtual Prototyping à
plusieurs niveaux d’abstraction.

Date :
20 au 23 Mars 2019 à Grenoble

Informations et réservation sur Atp Formation

UVM : Méthodologies de vérification pour IP et SoC

Cette formation s’adresse aux ingénieurs et chef de projet
désirant acquérir des approches et
méthodologies pour la vérification des “modules” (IPs) et de systèmes
sur puce (System on Chip). Elle comprend l’utilisation du langage SystemVerilog et des librairies UVM (Universal
Verification Methodology) pour la mise en œuvre de ces approches, la
présentation des principaux composants en
UVM ainsi que la création de tests
aux deux niveaux (IP et SoC).

Date : du 25 au 28 Mars 2019 à Sophia Antipolis

Informations et réservation sur ATP Formation

À propos de ATP Formation

Formation est une société de services spécialisée dans les formations
informatiques. Que ce soit en bureautique,
base de données, P.A.O, multimédia, C.A.O/D.A.O, gestion
commerciale/paye/comptabilité, gestion de projets, internet/intranet, langages
de programmation, systèmes d’exploitation/réseaux, elle déploie un large
éventail de plus de 300 formations. Basée sur Meylan, Atp Formation propose des
formations sur Meylan, Moirans et Sophia Antipolis.

Adrien Carmagnat of AEDVICES on Functional Safety at DVCon Europe


Adrien Carmagnat, AEDVICES’ latest recruit and an expert in verification methodologies, presented a paper on Keeping up with rapidly advancing safety standards at DVCon Europe in Munich last month (2018 Proceedings will be made available late January on the DVCon website).

AEDVICES Consulting is still recruiting new employees and trainees. If you would like to become our next new talent, please feel free to apply!

Adrien Carmagnat – DVCon Europe 2018

We were particularly pleased to present this work since (we believe) it makes a significant contribution to industry discussions on safety standards, and especially the part that Functional Verification has to play.

Furthermore, it is the fruition of an excellent collaboration with our customer, Melexis, and it’s been a great professional development experience for Adrien.

Adrien started as a trainee within AEDVICES Consulting eight months ago having majored in Embedded Systems at Polytech’Sophia. He has been trained on Advanced Verification Methodologies and during his internship he also developed skills in Verification IP and Tool Qualification. To recognise his excellent contribution to the project, we asked Adrien to step up to the plate and make the DVCon presentation, knowing there was a lot of verification expertise in the audience and that this would be a challenge!

Adrien was proud to make the presentation (and a bit nervous, too!). As he said afterwards: “I went on stage with a bit of stress, but it turned out to be easier than I’d expected! The attendees seemed interested. They asked probing questions and even shared some ideas that are prompting me to dig deeper into the subject. They may be useful for another paper next year – who knows! “



AEDVICES Consulting and ICONDA Solutions are coming together

AEDVICES Consulting, specialist in functional verification services, trainings and IP, is happy to welcome Andrew Betts as its new partner. He is joining our team to support functional verification sales and to strengthen our trainings catalogue.

Andrew is the owner of ICONDA Solutions and provides consulting, tranings and events for customer-facing teams.

This new collaboration is based on the reflexion that both activities are complementary. With AEDVICES Consulting’s expertise in functional verification and ICONDA’s expertise in many forms of trainings and facilitation, we hope to create a new synergy.

Presentation at DVCon Europe 2018

Adrien CARMAGNAT and François CERISIER, will present their paper during the new edition of DVCon Europe.

The Design and Verification Conference (DVCon) Europe is the leading European event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. This year, DVCon Europe will be held in Munich from October 24 to October 25.

To attend AEDVICES’ presentation:

Qualification of a Verification IP under Requirement based Verification standards: An Approach to the Verification of the Verification
Thursday October 25, 3:15pm – 4:45pm | Forum 5
Functional Safety Session

More information and registration : DVCon Europe website

Launch of the Galactic Partner Program from Breker Verification Systems

With long term relationship with Breker, AEDVICES Consulting is proud to  be part of this this Galactic program to enable the adoption of the Portable Stimulus Standard.

Breker Verification Systems Forms Galactic Partner Program to Accelerate Portable Stimulus Standard Ecosystem

Inaugural Consulting and Training Partners Include AEDVICES Consulting, Axiomise, Sunburst Design, T&VS, Willamette HDL

SAN JOSE, CALIF. –– May 2, 2018 –– Breker Verification Systems, the leading provider of Portable Stimulus, today announced formation of its Galactic™ Partner Program, naming five inaugural consulting and training companies to help accelerate the Portable Stimulus Standard Ecosystem.

The inaugural partners are AEDVICES ConsultingAxiomiseSunburst DesignTest and Verification Solutions (T&VS) and Willamette HDL, all recognized verification experts who manage and support large chip design and verification projects. Under terms of the program, each will work to build the ecosystem around the upcoming Accellera Portable Stimulus Standard, a standard means of specifying verification intent and behaviors reusable across target platforms, using the Breker tool suite.

Specifically, Sunburst Design and Willamette HDL will become Portable Stimulus Standard trainers based on the Breker tool suite, while AEDVICES Consulting, Axiomise, and T&VS will offer verification consulting services also based on TrekSoC™ and TrekUVM™.

“As the Portable Stimulus Standard moves fully into the verification flow, it becomes critically important to have experts available to help further adoption,” states Adnan Hamid, Breker’s founder and chief executive officer. “We selected the best-known and regarded industry experts to train the users about the value and benefits of Portable Stimulus.”

Future announcements about Breker’s Galactic Partner Program will include new members who supply verification intellectual property (VIP) and tools. For more information about the Galactic Partner Program, visit:

Breker first introduced a graph-based approach to test case generation in 2008, now known as Portable Stimulus. It gives chip design verification groups true Verification GPS (Graph-based, Portable, Shareable) with its Portable Stimulus solutions. Through the use of a Graph-based intent specification in an industry standard language, TrekSoC and TrekUVM offers proven Portability across verification platforms, scaling from IP to SoC for vertical reuse and SoC to post-silicon for horizontal reuse. It is Shareable across global diverse teams, project revisions and communication channels.

Breker’s tool suite is in use at large and mid-sized semiconductor companies worldwide on a variety of projects, including universal verification methodology (UVM) sequence synthesis and software-driven test generation from easy-to-author, graph-based representations and hardware/software scenario generation for emulation and system tests. Applications range from servers, networking, graphics processing units (GPUs) and field programmable gate arrays (FPGAs) to mobile and base stations for cellular wireless.
Breker is a founding member and an active participant of the Accellera Portable Stimulus Working Group (PSWG) and contributed a working C++ language representation for standardization efforts.

About Breker Verification Systems
Breker Verification Systems is the leading provider of Portable Stimulus solutions, a standard means to specify verification intent and behaviors reusable across target platforms, and the first company to introduce graph-based verification. Its Portable Stimulus suite of tools is Graph-based to make complex scenarios comprehensible, Portable, eliminating test redundancy across process, and Shareable to foster communication and reuse giving chip design verification groups true Verification GPS. Breker is privately held.